Silicon photonics, a technology where optical and electronic components are integrated on the same platform, is rapidly growing from a small niche to a technology enabler for higher speed data transmission in data centers, telecommunications, and high-performance computing.  Such fast growing field poses challenges and opportunities for the reliability and failure analysis engineers working in this field. This presentation overviews such challenges and opportunities encountered in the context of imec’s Silicon Photonics reliability research. For each developed device (being photo diodes, modulators, heaters, lasers, …), the related degradation mechanisms will be introduced together with their proposed testing and qualification methodologies and failure analysis challenges. The basics of each device will be introduced in detail such that the presentation can be followed by a broader audience with interests in reliability and failure analysis.

Micro-Electro-Mechanical Systems (MEMS) have revolutionized the semiconductor industry by seamlessly integrating electronics and mechanics to drive innovation in sensing and actuation at the microscopic scale. In a landscape shaped by the rapid evolution of artificial intelligence (AI), the topics of energy efficiency and sustainability have become increasingly crucial. MEMS emerge as key enablers of sustainability, offering precise sensing capabilities and enhanced energy efficiency. The keynote presentation explores the transformative potential of MEMS in reshaping our daily lives and propelling us towards a greener, more efficient future.

Wafer bonding is a key process for microsystems. The results are encapsulated chips as micro-electro-mechanical systems – wafer bonded MEMS. Wafer bonding is a mechanically strong and hermetic mounting of two wafers. Strength and hermeticity must be evaluated either as one-time characterisation, reliability testing, production monitoring or failure analysis. Here it is also interesting to know what happens inside wafer bonded chips – mechanical fractures, corrosion or delamination may occur but are hidden under the cap, inaccessible by optical or electron microscopy. In addition, there is not the one wafer bonding technology, but quite a lot, related to applications. Different methods can be used to analyse and understand the bond interface and what is inside the wafer bonded chip, e.g. infrared and scanning acoustic microscopy to inspect the bond area and internal structures, thermal or mechanical methods to check hermeticity, tensile or shear testing to check bond strength and opening wafer bonded chips for failure analysis, while non-destructive methods are of interest for production monitoring. How to use these methods also as combinations, is the topic of this presentation.

Pressure sensors based on silicon have proven to be robust for a wide range of operating conditions. However, maintaining the electromechanical device parameters as well as their stability is of crucial importance. To obtain high sensitivities, piezoresistive measurement bridges are used based on different implantation processes. At higher implantation doses dislocation networks are formed in the silicon substrate which affect directly or indirectly the sensor performance in a way so that p-n-junctions can be shorted. To analyse this behavior, these networks are investigated in detail by lock-in thermography and transmission electron microscopy in terms of the total dose of the implanted elements. It is found that depth and density of the network correlate with the applied dose. A special defect is found in highly doped structures with nanowire shaped structure which appears to be preferably aligned along the and crystal axes. These 1D defects can be correlated to hot spots measured in lock-in thermography. An element dispersive analysis revealed that these nanowires consist of a Fe/Ni core/shell heterostructure which can open electrical paths through p-n-junctions.

Integrated Circuit (IC) backside sample preparation is a critical step in semiconductor failure analysis eabling fault isolation to improve yield and investigate design modifications. Advanced probing techniques such as visible light laser voltage probing (vLVP) and electron beam (e-beam) probing require ultra-thin remaining silicon thinning (0-5 micron RST) to ensure signal access. However, this process compromises thermal conduction, potentially leading to overheating, altered device behavior, or destruction during testing. We demonstrate that testing ultra-thinned samples under dielectric fluid validates sample preparation techniques and be investigated for futher failure analysis techniques. This approach helps to remove barriers to ultra-thinning adoption by addressing concerns over device degradation. Fully ultra thinned and tested IC samples can then undergo specific testing such as e-beam probing in vacuum environments.

Globalfoundries’ 22nm FDSOI (22FDX®) technology offers full SoC integration including digital, analog and RF. It combines high performance and ultra-low power. With body-biasing it is possible to adjust the device performance to lower power at same frequency or increase performance at same power. Despite all the great features, it brings also some challenges for physical failure analysis, especially on device level. Due to the small transistor size, failure analysis by cross sectioning with SEM/FIB slice and view is difficult to find a defect in the SEM image. Conventional methods to detect faulty devices in a larger area (e.g. leaky gate, etc.) with passive voltage contrast is not possible, because a FDSOI transistor is isolated from the bulk Silicon by a buried oxide layer. Therefore, Nanoprobing plays an important role for fault isolation and electrical device characterization. Unfortunately, the Electron Beam of an SEM based Nanoprobing system leads to a degradation of the transistors by charging. In my talk I will provide insights on sample preparation, Nanoprobing parameters, future requirements and alternatives like an AFM based probing system.

Ongoing advances in functionality and computational performance of microelectronic devices require continuation in the developments in the underlying technologies for e.g., interconnect and packaging to allow for efficient inter-chip communication and effective broad band integration in terms of frequency and data transfer. The resulting increase in the overall complexity is accompanied by decreasing physical feature sizes and an expansion of the assembly into the third spatial dimension. As a consequence, inspection for defects is required to be sufficiently sensitive to uncover defects of reduced size and weaker emissions and to allow localization in the three-dimensional space. The work presented here addresses research and developments conducted to increase sensitivity and to enable for a true spatial resolution of lock-in thermography as a technique for defect detection and localization. Based on the analysis of the spatial phase distribution estimated from acquired thermal signals recorded from microelectronic devices thermal sources inside the microelectronic structures have been sensed and precisely located in all three spatial dimensions inside the sample.

The emergence of three-dimensional (3D) semiconductor devices has increased the importance of thermal imaging techniques. We present a dual-capability system combining thermo-reflectance and thermal lock-in imaging (LIT) for high-speed, highly sensitive thermal analysis. We evaluate the hotspot detection capabilities of two-wavelength thermo-reflectance compared to LIT, including results from actual failure analysis cases. Our findings demonstrate the effectiveness of thermo-reflectance detection (TD) imaging for 3D devices where direct optical access to active layers is limited, such as 3D NAND flash memory and BSP-DN structured devices. This approach offers a promising solution for the thermal characterization of complex 3D semiconductor architectures.

Lockin Thermography is a great failure analysis technique to investigate shorts or in general resistive connections. By applying an RF-stimulus, it will be shown in this presentation that the technique can be made applicable for highly resistive and even (DC-) open connections. The stimulus itself will be discussed, as well as the experimental setup. Then, the RF-LIT technique will be demonstrated on a number of practical use cases, including MEMS and RDL, in order to show its applicability. In order to gain a better understanding why it works, a simulation model will be constructed. This will then subsequently be linked to experiments on MEMS which offer further insights on RF-LIT.

The increasing demand for energy-efficient devices, such as electric vehicles (EVs) and renewable energy sources, highlights the importance of power devices for efficient energy management and conversion. New materials like SiC and GaN offer multiple advanteges compared to traditional Si-based devices. Hamamatsu Photonics K.K. (HPK) has introduced Optical Fault Isolation solutions to the semiconductor failure analysis market. HPK’s new PHEMOS-X high voltage solution supports up to 5kV without discharge, ensuring safety. Additionally, HPK is developing a low-temperature solution to prevent condensation with the current prober on PHEMOS-X. HPK also introduces Green OBIRCH for SiC devices. The rise of three-dimensional (3D) semiconductor devices has increased the need for advanced thermal imaging techniques. HPK presents a dual-capability system combining thermo-reflectance and thermal lock-in imaging (LIT) for high-speed, sensitive thermal analysis. This system effectively detects hotspots in 3D devices, such as 3D NAND flash memory and BSP-DN structured devices, offering a promising solution for thermal characterization of complex 3D semiconductor architectures.

Lock-in thermography allows failure inspection in electronics by detection of inhomogeneous temperature distribution and local power loss in 2 dimensional and 3 dimensional way. This is achieved by using the shortest measurement times combined with a high-performance and high resolution thermographic camera and a specialised lock-in procedure. The power supply for this process is clocked with a synchronisation module and failures that produce mK or even μK differences are reliably detected.

Smallest defects like point and line shunts, oxide failures, transistor and diode failures on a PCB surface and in IC´s can be detected and displayed in x and y positions. Additionally, it is possible to analyse stacked-die packages or multi-chip modules in z-direction with merely changing the lock-in frequency.

In this work the combination of new system hardware and software functions are shown to use HD lock-in thermography in a very flexible way for different components and for fast detection of electrical failures.

Electrical probing of transistors at advanced technology nodes requires precise alignment of the probe and the sample. This is typically performed within a scanning electron microscope (SEM) to visualize the probe and sample. Alignment is generally based on visual feedback from SEM images, a process that is time-consuming. Moreover, continuous exposure to the electron beam can result in carbon deposition and sample charging. Carbon deposition can pose significant challenges by increasing the contact resistance between the sample and the probe. Additionally, sample charging may alter its physical properties or even cause permanent damage. Consequently, it is crucial to minimize charging as much as possible when measuring the intrinsic electrical properties of the sample. This presentation will demonstrate methods for reducing the electron dose to an absolute minimum during nanoprobing.

When analyzing semiconductor devices, particularly for failure or construction analysis, mechanical sample preparation is crucial. The main factor for successful preparation is to use the right tools that match the device’s complexity.
There is a growing belief that these complex devices require high-precision beam tools. However, these tools are often not designed for large-area analysis or high throughput. In contrast, mechanical sample preparation provides several advantages.
• High Throughput: Mechanical methods can process samples more quickly.
• Precision Over Large Areas: They maintain a high level of precision across larger surfaces.
• Cost-Effectiveness: Mechanical preparation is significantly less expensive compared to other methods, such as plasma focused ion beam (FIB) sample preparation.
In this talk, the focus will be on the benefits of using mechanical sample preparation tools for large-area analysis, specifically in the context of complex power silicon carbide (SiC) devices.

Integrating femtosecond laser technology has significantly advanced sample preparation, offering unprecedented precision and speed. The microPREP® PRO FEMTO system exemplifies this innovation, utilizing ultrashort pulse lasers to enable athermal ablation with minimal heat-affected zones. This capability ensures the preservation of sample integrity while allowing for high-precision, high-speed preparation for various techniques, including SEM, APT, and micromechanical testing. The system improves throughput without sacrificing quality by reducing preparation time from hours to minutes.
Equipped with advanced features such as a telecentric objective and CO2 Snow Jet cleaning system, the microPREP® PRO FEMTO enhances the cleanliness and accuracy of prepared samples, which is crucial for atomic-scale analysis. Its seamless integration with ion-based systems, such as FIB and BIB, maximizes sample preparation efficiency while maintaining exceptional precision. This laser-based approach is transforming materials science and semiconductor research by offering an efficient, scalable, and precise solution for advanced sample preparation.

With more than four decades innovating physical and electrical analysis solutions for the electronics industry. Thermo Fisher Scientific is one of the world’s premier providers of ultra-highresolution tools for imaging and analysis at the nanoscale.
Today, a more connected, more autonomous, and smarter world is translating into a huge demand for semiconductors in everything from cars to cellphones to refrigerators. The confluence of artificial intelligence, cloud, connectivity and intelligent edge are driving continued innovation in semiconductor to meet consumer’s needs. However, shrinking geometries, new materials, and novel 3D architectures make these continual improvements increasingly more challenging. Thermo Fisher provides the broadest portfolio of semiconductor metrology, characterization and fault analysis instruments to accelerate pathfinding and development, maximize yields, and ensure the production of high-quality devices that meet current and future industry demands.

Thermo Fisher’s next-generation products focus on advanced analytical capabilities for failure analysis, yield learning, and process control.

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At the forefront of technological progress, TESCAN’s advanced suite of tools—including Focused Ion Beam-Scanning Electron Microscopy (FIB-SEM), Scanning Transmission Electron Microscopy (STEM), and high-resolution micro-Computed Tomography (micro-CT)—empower researchers and engineers to explore, analyze, and optimize semiconductor materials and structures with unmatched clarity and precision. Our state-of-the-art solutions are designed to meet the ever-evolving demands of the semiconductor industry, enabling breakthrough insights in material characterization, failure analysis, and process development. Whether you’re pioneering the next generation of DRAM memory technologies, pushing the boundaries of 3D NAND architecture, or enhancing performance in advanced logic devices, TESCAN provides the critical imaging and analytical capabilities you need. Our technologies also play a vital role in the development and refinement of power semiconductor devices, ensuring they meet rigorous efficiency and reliability standards.

This tutorial will review recent results concerning deep levels in GaN HEMT, their physical origin, their effects on device operation, the experimental techniques adopted for their characterization. Scaling of GaN HEMTs for microwave and millimeter-wave applications will be discussed in relation with dispersion and short-channel effects. Models of recoverable and permanent degradation due to hot electron effects will be presented. Finally, consolidated results and open issues concerning thermally-activated failure modes and mechanisms of GaN HEMTs will be presented.

III-nitrides has been gaining increased attention in the power electronics industry due to its advantageous chemical, mechanical and electrical properties marking an obvious successor in many power management applications. Based on wide band gap material, GaN high electron mobility transistor (HEMT) offers high electrical breakdown as well as low on-resistance thanks to naturally occurring two-dimensional electron gas. Two GaN HEMT topologies, namely, depletion mode (D-mode) and enhancement mode (E-mode) already gained commercial footprint in power electronics and are expected to show the highest CAGR in the industry.
E-mode topology prevails today mainly due to its simplicity on the application level. However, we argue that D-mode devices will retain several advantages, particularly in the higher power segments, which will ultimately keep both e-mode and d-mode devices relevant pending application segments.
A comparison of E-mode and D-mode devices is presented in this paper. Device technology, application and reliability aspects are covered highlighting proc and cons in regards of target application segment. Based on those aspects, high-power and high-performance applications.

Understanding the distribution of crystal defects is an important topic for semiconductor materials. This is particularly challenging for gallium nitride on silicon (GaN-on-Si) as the defects have a density of ~5×10^9 cm-3. Understanding – and ultimately monitoring – crystal defects at this density is an unsolved problem.
Transmission electron microscopy (TEM) is the gold standard for understanding crystal defects, and it has a body of understanding going back 60+ years, but the equipment expense and low sample throughput make it unattractive for any statistical studies of crystal defects. More recently, scanning electron microscopy (SEM) has shown promise for quantitative defect measurements in GaN, using electron channelling contrast imaging (ECCI).
In this work, we have performed a detailed study of the same 132 dislocations in a GaN sample with both SEM and TEM. The dislocation type (a-type, c-type, a+c-type) was determined with both methods. Only three measurements differed between the two methods. This work paves the way for ECCI in SEM to be ramped-up as a monitoring tool for dislocation type in GaN, at least for epitaxy development.

Cathodoluminescence (CL) consists in the analysis of the light emitted in the UV-IR range by a material upon its excitation with an electron beam. This technique is particularly useful in compound semiconductors, such as GaN, SiC and InGaAsP, where it allows local probing of material properties.
In CL panchromatic images, defects such as threading dislocations (TDs), stacking faults and slide planes appear as dark features because of non-radiative recombinations. Variations in point defect concentration can also be revealed. In CL spectroscopy, the emission wavelength provides additional information such as the type of stacking fault in SiC, the composition of alloys such as AlGaN, layer thickness or strain level.
This work first reviews defect characterization in compound semiconductors by cathodoluminescence, then focuses on the characterization of defects in GaN HEMT devices.

The clear correlation of defect localization by Electroluminescence to nanometer sized defects at Schottky gate contacts of GaN HEMTs are always challenging and limiting the root cause analysis of the stress related electrical degradation of the devices. In this paper a novel approach combining large area planar TEM defect screening followed by cross sectional preparation at identified defect sites is demonstrated to get access to relevant structural damages at the gate. The analysis flow is applied for normally-on GaN HEMT devices with an increased leakage at the Schottky gates observed after electrical stressing. To initiate electrical active degradation these devices were stressed up to significant changes in the electrical performance and then Electroluminescence spots were detected identifying possible defect positions. Metal intrusions into the AlGaN/ GaN stack underneath the Schottky gate contacts of only 20 nm size could be found by the newly combined planar/ cross-sectional analysis flow in good correlation to the EL spot positions. Analytical TEM investigations of the defects reveal Pt and Au inside the semiconductor reaching the 2DEG at a threading dislocation of HEMT.

Infrared (IR) microscopy is a powerful tool for defect analysis in Micro-Electro-Mechanical Systems (MEMS) and Application-Specific Integrated Circuit (ASIC) devices. A steep increase in IR analysis demand combined with the need for high-resolution images generates a vast amount of data. This makes manual image acquisition and inspection nearly impossible or would require an extremely high effort in time and manpower.

The solution we present leverages the automation capability of our IR microscopes and provides a streamlined acquisition and analysis pipeline for IR microscopy analysis for single chips, batches of chips, and full wafers. Automated imaging scans devices at high magnification, stitching the resulting images into high-resolution IR image composites. These composites are then processed by state-of-the-art defect prediction models to accurately identify and mark defects. Our IR microscopy workflow significantly increases throughput, reduces analysis time, and improves the consistency and accuracy of defect detection in our semiconductor devices.

This work has been funded by the German “Bundesministerium für Bildung und Forschung (BMBF)” in the project FA2IR.

This presentation focuses on leveraging machine signal data from wire bond machines by building data-driven solutions to enhance root cause analysis efficiency and real-time quality control in semiconductor wire bonding. Traditional root cause analysis is time-consuming, labor intensive and performed in hindsight. We performed experiments at NXP Semiconductors N.V. that mimicked wire bonding problems caused by forming gas, and subsequently used the resulting real-world data to overcome the traditional root cause analysis challenges. We show that random forest classification models can successfully differentiate between standard and problematic wire bond manufacturing conditions, identifying significant machine-signal-related features associated with forming gas issues. The study demonstrates the effectiveness of linking machine-signal-related features to root causes, enabling proactive detection of potential failures during wire bonding.

Arivis Cloud is a web platform that enables failure analysts & other customers to leverage the power of Deep Learning without any prior ML/coding experience. It supports the most common microscopy image formats and can be used to solve a wide range of applications. Users can create and annotate datasets as well as train AI models in a collaborative way. In this talk, we will present some of the improvements that we have implemented in the last year within the EU project FA2IR. Also, we are going to show a live demo with tangible examples.

Failure analysis (FA) in microelectronics is becoming increasingly complex due to the miniaturization of components and the growing need for precise defect detection. Traditional FA workflows often rely on manual inspection, which are time-intensive and prone to variability. This study explores the integration of digital workflows and machine learning (ML) techniques to enhance FA efficiency.

An ML-based approach was developed for automated image analysis, ensuring consistency across multiple samples and integrating seamlessly into an external microscopy software platform for a fully digital workflow. The model demonstrated improved detection accuracy, ranging from 88% to 96%, compared to conventional image processing techniques, while also being 30x to 40x more time-efficient. This advancement enables early identification of defects, enhancing the overall FA process. Additionally, an ML pipeline was implemented to facilitate automated feature extraction and defect localization, further streamlining analysis. These ML-driven methods significantly optimize FA workflows by reducing manual effort, increasing defect detection precision, and enabling data-driven decision-making.

AI-driven failure analysis in acoustic microscopy is often constrained by measurement setup dependencies, requiring models to be trained for specific configurations – such as transducer type, focus distance, or excitation energy. Furthermore, traditional workflows rely on labeled training data containing defect and non-defect scans. This presentation introduces an anomaly detection approach that reduces the need for defect-labeled training data. By training solely on non-defective components, the model can detect deviations in new, unknown samples of the same type, enabling defect identification without prior knowledge of specific failure modes.
Beyond this, we explore methods to further generalize AI models for acoustic microscopy. Typically, even minor changes in measurement settings can significantly degrade model performance. We present initial steps to eliminate these setup-specific dependencies, allowing models to maintain accuracy across different scanning conditions – even ones, which are not included in the training data. This advancement has the potential to streamline AI-based failure analysis workflows and enhance the adaptability of machine learning models in FA.

The automation of nanoprobing application relies on the accurate detection of probe tips in scanning electron microscope (SEM) images. This work explores the application of deep learning models to automate and improve this critical process. Different models such as Mask R-CNN, YOLOv8 and RTMDet, trained on a specialized dataset, are used to accurately detect, segment and localize probe tips in SEM images, even under challenging conditions. Results show that these models have the potential to improve the automation of nanoprobing workflows, particularly in automatic tip positioning and crash prevention. Future work will focus on production-level deployment and the integration of tracking algorithms.

Failure Analysis (FA) is critical for fast time-to-market and semiconductor reliability, yet structuring FA knowledge to align with FAIR principles (Findable, Accessible, Interoperable, Reusable) remains a challenge. Inspired by medical ontologies, we propose a Failure Analysis Ontology (FAO) to represent FA knowledge in a machine- and human-readable format. This enables knowledge graphs that support AI-driven searches and analytics, delivering faster and more accurate insights across the FA process. The FAO spans the entire FA workflow, linking FA data with production information such as technology details and FA equipment. This unified framework ensures traceability, smarter analysis, and streamlined problem-solving throughout the semiconductor lifecycle.

As part of the EU-funded FA2IR project, we collaborate with European semiconductor manufacturers, FA service providers, and tool suppliers to create a modular, open-source FA ontology. It includes an open-source base and a standardized proprietary extension, enabling secure internal data integration. Shared failure codes and standardized datasets ensure interoperability and boost FA efficiency across the industry.