Martin Igarashi

The semiconductor industry still has the compelling need to cost effectively produce higher performance computing devices such as AI applications.  The industry’s answer is to adopted chiplet-based architectures. The chiplet architecture offers the advantages of cost and performance improvements by enabling high bandwidth, low-latency interconnects between devices. Subsequently, when such complex heterogeneous integration semiconductor packages fail, the challenge of isolating faults in such complex structure would become surmountable. An electrical fault isolation tool that can help with such D2D defect localization is the EOTPR 4500 system. It has the sensitivity and sub-5 µm distance-to-defect fault isolation accuracy to detect impedance changes in I/O shorts and opens. The DUT holder for the EOTPR 4500 system is designed to accommodate the substrate size as large as 150mm × 150 mm. With increased stage accuracy and microscope resolution, the EOTPR 4500 system can probe contacts as small as 3 µm in diameter by using specially designed micro-contact needle-nosed probe tips. This presentation will discuss how EOTPR 4500 was used to isolate defects on a D2D interconnect trace of chiplet type semiconductor packages using local silicon bridge.

Martin has over 30 years of experience in semiconductor industry with background in ASIC and CMOS image sensor design and fabrication, test and measurement, front end wafer processing, photolithography, and laser material processing.   He majored in applied math, and minored in computer science, and computer engineering at the University of California at Santa Barbara.  He has worked for companies such as Applied Materials, Tektronix, ETEC Systems, Toppan, and Electro Scientific Industries.  He currently serves as VP of Semiconductor Business at TeraView LTD. Since 2010. While TeraView is based in Cambridge, UK; Martin is based in Portland, Oregon.