Michael DiBattista

Integrated Circuit (IC) backside sample preparation is a critical step in semiconductor failure analysis eabling fault isolation to improve yield and investigate design modifications. Advanced probing techniques such as visible light laser voltage probing (vLVP) and electron beam (e-beam) probing require ultra-thin remaining silicon thinning (0-5 micron RST) to ensure signal access. However, this process compromises thermal conduction, potentially leading to overheating, altered device behavior, or destruction during testing. We demonstrate that testing ultra-thinned samples under dielectric fluid validates sample preparation techniques and be investigated for futher failure analysis techniques. This approach helps to remove barriers to ultra-thinning adoption by addressing concerns over device degradation. Fully ultra thinned and tested IC samples can then undergo specific testing such as e-beam probing in vacuum environments.

Michael received his Ph.D., M.S.E. and B.S.E. in Chemical Engineering from the University of Michigan. His thesis work was based on characterizing thin film chemical sensors and elevated temperature analysis of thin films with AFM. He has worked in the semiconductor industry for 24 years at Intel Corp, FEI Company, and Qualcomm and focused on developing tools and technology to support physical failure analysis and FIB based circuit modification. Michael has more than 20 publications in the semiconductor and microscopy fields and has 10 issued patents. He is currently focused on deprocessing of semiconductor devices and laser assisted chemical deposition at Varioscale, Inc.