Georg Spanring

In 3D integrated circuit (IC) design, Through-Silicon Vias (TSVs) form vertical metal connections that pass entirely through a silicon wafer or die. They enable stacking and direct integration of multiple semiconductor devices in a single package. Fault isolation in TSVs, along with sample preparation, poses significant challenges to Failure Analysis (FA).
In this contribution, an FA case is presented in which Bulk Micro Defects (BMDs) in the silicon substrate led to needle-shaped silicon remnants on TSV sidewalls after the TSV etching process, causing electrical shorts between the substrate and the sidewall metallization. A thorough understanding of the root cause was achieved, enabling the implementation of effective corrective actions.
The fault isolation process, including Optical Beam Induced Resistance Change (OBIRCH), Focused Ion Beam (FIB) techniques, and Transmission Electron Microscopy (TEM) analysis, is described in detail, demonstrating its applicability for identifying leakage paths in TSVs.

I earned my Diploma in Applied Physics from Graz University of Technology in 2005. Shortly after graduating, I joined ams-OSRAM AG in Premstaetten, where I have been part of the Failure Analysis Department for nearly a decade. My work primarily focuses on advanced electron microscopy techniques, with a particular emphasis on FIB (Focused Ion Beam) and TEM (Transmission Electron Microscopy).