CAM-Workshop Program 2024
Day 1 (4. June 2024)
Session A: Welcome and Keynotes
| 09:00 – 09:20 | Prof. Dr. Erica Lilleodden / Frank Altmann | Fraunhofer IMWS (DE) | Welcome |
| 09:20 – 10:00 | Frank Fournel | CEA-Leti (F) | Keynote: Characterisation needs in wafer-to-wafer and die-to-wafer direct bonding |
| 10:00 – 10:40 | Anton Chichkov | Chips Joint Undertaking (BE) | Keynote: EU Chips Act – An Introduction |
Session B: Heterogeneous Integration
| 11:20 – 11:40 | Serena Iacovo | IMEC (BE) | A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage |
| 11:40 – 12:00 | Sebastian Quednau | NanoWired (DE) | Assembly and Interconnection Technology with Nanowires |
| 12:00 – 12:20 | Torsten Grawunder | Swissbit Germany AG (DE) | Open Advanced Packaging / Micro Integration Foundry as a model for one manufacturing platform with integrated LAB-in-the-FAB concept |
| 12:20 – 12:40 | Sebastian Brand | Fraunhofer IMWS (DE) | Approaches in high resolution non-destructive defect localization to meet current and future integration challenges |
| 12:40 – 13:00 | Jan Proschwitz | Intel (DE) | Robustnes and reliability testing for heterointegration |
| 13:00 – 13:20 | Dirk Schade | XYZTec (DE) | Revolutionizing semiconductor testing: The power of automation in testing chiplets |
Session C: Novel Failure Analysis Techniques
| 14:40 – 15:00 | Sven Kayser | IONTOF GmbH (DE) | Hybrid SIMS: New possibilities for advanced semiconductor structure analysis with Self-Focusing SIMS |
| 15:00 – 15:20 | Wenbing Yun | Sigray Inc.(US) | X-ray Assisted Device Alteration (XADA) for Future Generations of ICs with Backside Power Distribution Network |
| 15:20 – 15:40 | Rene Hammer | Point Electronic GmbH (DE) | Advances in EFA with color coded multi-channel nanoprobing |
| 15:40 – 16:00 | Thomas Adlmaier | Infineon Technologies Dresden GmbH (DE) | Advancing the Quantification Workflow for 2D Charge Carrier Profiling by Scanning Spreading Resistance Microscopy |
| 16:00 – 16:20 | Anjanashree RM Sharma | IMEC and KU Leuven (BE) | Failure analysis methodologies for silicon photonics devices |
Session D: Panel Discussion
Day 2 (5. June 2024)
Session E: Tutorial
| 08:00 – 09:00 | Michael Kögel | Fraunhofer IMWS (DE) | Machine Learning Based Data and Signal Analysis Methods for the Application in Failure Analysis |
Session F: Wide Band Gap Power Electronics
| 09:40 – 10:20 | Peter Friedrichs | Infineon Technologies AG (DE) | Keynote: SiC power devices and related robustness and reliability aspects |
| 10:20 – 10:40 | Habib Mustain | Heraeus (USA) | Robustness for power electronic packaging |
| 10:40 – 11:00 | Dick Scholten | Robert Bosch GmbH (DE) | Gate-switching instability in silicon carbide power MOSFET’s |
| 11:00 – 11:20 | Andreas Graff | Fraunhofer IWMS (DE) | Integration of free-standing single crystal diamond (SCD) nanomembranes in ultra-wide bandgap electronics |
| 11:20 – 11:40 | Antoine Reverdy | Sector Technologies (FR) | Power devices Failure Analysis Use Cases Using High voltage OBIRCh workflows |
Session G: Failure Analysis Workflows and Digitalization
| 13:00 – 13:40 | Prof. Dr. Zhiheng Huang | Sun Yat-sen University (CN) | Keynote: Applied Microstructure for AI: From Electrons to Devices & From Diagnostics to Informatics |
| 13:40 – 14:00 | Allen Gu | Carl Zeiss Research Microscopy Solutions (US) | An Artificial Intelligence Powered Reconstruction and Metrology Workflow for Semiconductor Packaging Development using High-Resolution 3D X-ray Microscopy |
| 14:00 – 14:20 | Amit Kumar Choudhary | Matworks GmbH (DE) | ML assisted defect detection for reliable failure analysis in microelectronic components |
| 14:20 – 14:40 | Fabian Rudau | Robert Bosch GmbH (DE) | In Depth Logic Analysis on Digital Designs |
| 14:40 – 15:00 | Christian Hollerith | Infineon AG (DE) | Integrated Workflows for Failure Analysis |
| 15:00 – 15:20 | Libor Strakoš | Thermo Fisher Scientific (CZ) | In-situ AFM-in-(FIB)SEM workflow for site-specific & correlative failure analysis of semiconductors |
| 15:20 – 15:40 | Oscar Recalde | Kleindiek Nanotechnik GmbH (DE) | Automated SEM/EBIC Workflow for Wafer Level Failure Analysis |