Heterogeneous Integration (HI) is pivotal for advancing next-generation electronic systems, yet it introduces significant challenges in design, manufacturing, and long-term reliability due to increased complexity and diverse material interfaces. This presentation introduces AI/ML-driven paradigms to address these essential challenges, aligning with strategic industry directions like the IEEE EPS Heterogeneous Integration Roadmap.

I will first explore the development of a Digital Twin focused on predicting solder degradation in HI components, drawing insights and methodologies from the e²LEAD project. This twin leverages multi-physics simulations and machine learning to model the evolution of accumulate plastic strain. Next, we delve into Intelligent Reliability, showcasing AI/ML-based approaches to enhance predictive maintenance. This section emphasizes anomaly detection, and AI-driven test strategies. Finally, I will present how AI/ML transforms Failure Analysis, demonstrating automated defect detection and classification using computer vision, and AI-assisted root cause identification to significantly accelerate and improve the accuracy of investigations in complex HI systems.

Together, these AI/ML-powered approaches offer a holistic framework to accelerate the design, manufacturing, and reliability assurance of heterogeneously integrated electronic components.

As industries expand their use of silicon photonic integrated circuits (PICs), it is imperative that manufacturers be able to continuously improve the quality of their manufactured PICs. To do so, fault isolation of unwanted defects is necessary.
Electrical fault isolation tools are typically comprised of a photoemission camera, thermal camera, and a laser scanning microscopy system. These same isolation tools can be used to perform fault isolation on PICs. The photoemission camera captures short-wave infrared light, capable of capturing three photonic light input wavelengths (O, C, and L-bands) and can be used to isolate any areas within a waveguide feature that the input/signal light is being emitted and lost. The thermal camera, with ability to capture mid-wave and long-wave infrared emissions is useful in mapping dynamic and steady state temperatures of PICs integrated and co-packaged with electrical circuits.
The presentation will discuss challenges of using state of the art 300nm electrical fault isolation tools for PICs including variations of electro-optical test setup, imaging challenges in 3D co-packaged samples, and the limitations of laser scanning microscopy.

Photonics components exhibit at least electrical and optical functional properties, as in transceivers or image sensors for instance. In addition, mechanical functions may come to the fore, as it is the case e.g.with mechanically controllable filters or micro scanners. Characterization and testing methods are therefore highly complex, with the generation and detection of electrical signals and optical radiation, the measurement of motion, and material and surface properties playing a major role.
Photonics is becoming commercially attractive for high-speed communication, imaging across a wide wavelength range (UV… MIR), sensor technology, and even for interconnecting chiplets within a microsystem, as well as for quantum computing. The development of efficient testing methods is therefore becoming increasingly important. This contribution discusses various methods for characterizing different photonic components used in sensor technology, information transmission, and quantum technology, illustrating these with examples and addressing the measurement of electrical, optical, and mechanical properties. Finally, it explores a concept for a universally applicable photonic testing system.

Advanced microelectronics failure analysis and metrology require rapid access through heterogeneous stacks (mold compound, underfill, metals, dielectrics, silicon). Tescan FemtoChisel is an ultrashort-pulsed laser platform for high-throughput sample preparation, focused on decapsulation/delayering and millimeter-scale cross-sectioning. It removes encapsulants to expose die/package regions for optical/SEM inspection and probing, performs stepwise delayering to reveal circuitry, silicon, and interposer metallization, and produces large-area cross sections with high feature visibility. These capabilities are enabled by intelligent multigas processing (during/between scans) to control plume, cooling, and debris evacuation, plus a removable laser protective layer (LPL) that suppresses peripheral beam interactions and protects nearby features during high-energy ablation. Together they reduce redeposition and collateral damage, expanding the usable high-fluence window for scalable advanced-package FA.

NN

Diamond is an ultra-wide bandgap semiconductor material, whose electric properties make it a great choice as p-type material for device integration. Further, diamond possesses the highest thermal conductivity, which also makes it a great choice for use and integration within thermal cooling solutions.

This talk discusses a familiar of diamond-based technologies that were developed by Fraunhofer USA, Center Midwest, Fraunhofer IFAM and Fraunhofer IMWS to address cooling challenges within the various components of a semiconductor system:
(1) A single-crystalline diamond nanomembrane technology is presented, which enables device integration of boron-doped diamond layers with other semiconductor materials through means of heterointegration.
(2) A polycrystalline diamond nanomembrane technology portfolio is presented, which can be used as thermal interface material or as heatsink.
(3) A copper-diamond composite material, produced by gel-casting and spark-plasma-sintering, that can be used as heatsink with thermal conductivity exceeding that of copper by 3x is showcased.

Threading dislocations (TDs) are critical crystalline defects in GaN-based materials, significantly impacting the performance, reliability, and lifetime of electronic and optoelectronic devices. We present Revelios, a semi-automated, non-destructive crystalline defect metrology software prototype based on electron channeling contrast imaging (ECCI). Revelios SW prototype enables large-area acquisition, automated stitching, detection and classification of TDs into a-, c-, and a+c-types. Dislocation type is determined by combining data acquired at different diffraction conditions and analyzing the black-white contrast orientation with respect to the set diffraction vector. Validation against expert manual evaluation shows a detection accuracy of 94% and a classification accuracy of 79%. These results demonstrate that Revelios SW prototype provides a robust and scalable solution for high-throughput GaN defect metrology and could be suitable for epitaxial process optimization and manufacturing control. Automation significantly increases throughput and reliability, supports efficient quantitative TD analysis, and makes the methodology accessible to less experienced users.

The semiconductor industry has entered a new era, driven by agentive Artificial Intelligence (AI) and large language models.  AI models have scaled from millions to trillions of parameters, requiring datacenters with many thousands of GPU networked together and working as one giant chip, especially for model training. This complexity demands unprecedented silicon quality, reliability, and advanced failure analysis (FA).

Recent innovations such as 2.5D/3D integration, backside power delivery, and co-packaged optics introduce new defect mechanisms requiring even more advanced fault isolation and root cause determination methodologies.

This talk will provide an update regarding the development of advanced probing and non-destructive fault-localization techniques and the required test infrastructure. Success depends on deep collaboration across fabs, chip- and package-design, DFT, FA tool vendors and research organizations.

We describe a magnetic inverse that can extract a 3D current path from a magnetic field image of the path. To evaluate performance, we processed hundreds of simulated images with accurately known parameters and examined a few real images for comparison. The simulated images were built with 1-10 segments that could meander between 1-3 layers. Segments were aligned along the x or y directions, or 45 degrees to x and y. Some images had a small overall rotation. Each image had random noise with a standard deviation of 0.1 nT and some images included random position errors with a standard deviation of 0.1 micron (typical for MAGMA SQUID microscope). Typical path and image parameters were sample-sensor separations z between 0.02 and 1 mm, segment lengths between 0.05 and 2 mm, and current between 0.1 and 2 mA. We find that the vertical and lateral resolution are comparable, proportional to the depth z of the current path, and inversely proportional to the total signal-to-noise ratio (S/N) of the image. For high enough S/N, the vertical and lateral resolution was typically better than z/1000, implying sub-micron vertical and lateral localization of circuit paths out to depths z ~ 1 mm.

The transition to advanced 3D integrated circuits and system-in-package designs is creating major challenges for fault detection, yield optimisation, and process understanding. Existing inspection and failure-analysis methods often cannot provide the non-invasive, depth-resolved electrical information needed to study complex current paths and buried faults in these architectures.

We are developing a Quantum Diamond Magnetic Microscope based on NV-diamond sensors for real-time magnetic imaging of integrated circuits. Our goal is to enable non-invasive 3D current mapping with sub-micron resolution, high sensitivity, and high acquisition speed, beyond the limits of conventional inspection tools and current wide-field quantum sensing systems.

We have built first laboratory prototypes and demonstrated targeted single-pixel sensitivities of 5–10 nT/√Hz. In the talk, I will present the system concept, discuss the current prototype status, and show first measurement results on test structures and semiconductor samples. I will also outline the remaining engineering steps toward a robust instrument for semiconductor metrology and failure analysis.

This presentation introduces Electro-Optic Terahertz Pulse Reflectometry (EOTPR) as a non-destructive method for the localization of electrical opens and shorts within semiconductor device packages. EOTPR operates by generating a short electrical pulse, injecting it into the device, and analyzing the time-dependent reflection patterns to locate interruptions. This technique is effective for determining both the presence and position of package failures.
In this presentation, we show application examples for localizing opens in various packages: complex BGA package, flex circuit board, D2PAK power package, and a power module for electromobility.
Together with the University of Stuttgart we investigated the D2PAK power package deeper concerning the amount of open bond wires. By using a principal component analysis we were able to distinguish, if one, two or three bond wires contribute to the electrical dysfunctionality.
For the EOTPR analysis, it is necessary to work with references. For this, electrical opens often have to be prepared inside the package. This is done, for example, by removing the mold compound, subsequently cutting traces or bond wires, and then resealing packages.

Nanoprobing imaging equipment for Electron Beam Absorbed Current/Resistive Contrast Imaging (EBAC/RCI) and Electron Beam Induced Current (EBIC) techniques is widely used in the semiconductor industry for process control and development. As components of electronic devices become smaller, the impact of electron beam irradiation becomes more severe, and the use of low beam acceleration voltages coupled with low beam current is recommended to avoid transistor damage [1-2]. Necessity for lower beam current leads to much reduced nanoprobing imaging signals, and thus lower overall signal-to-noise ratio. In this article, we describe the development of a novel pA noise-level amplifier for RCI and EBIC measurements of high impedance samples. A peak-to-peak noise level of 3 pA is shown here with this new amplifier. We compare experimental performance of this novel low noise amplifier to an established reference amplifier and illustrate the gained benefits and new limits for RCI measurements.

[1] A. Qiu, W. Lowe, M. Arora, Int. Symp. for Testing and Failure Analysis. Vol. 82747 ASM Int. (2019)
[2] Y. Mitsui, T. Sunaoshi, J. C. Lee, Microelectronics Reliability 49.9-11 (2009): 1182-1187

Ultra-thin, precisely targeted lamella preparation on advanced IC devices has traditionally been considered a Ga-FIB application. However, recent advances in semiconductor processing now require gallium-free lamella preparation, particularly at the latest technology nodes. In this study, we demonstrate how high-quality, on-target lamellae can be successfully prepared using Multi-ion species plasma FIB, meeting the demands of advanced device analysis without introducing Gallium into the system. The talk will focusing on procedures to make the lamella as well as qualifying the final result with TEM.

NN

Scanning Acoustic Microscopy (SAM) is widely used in semiconductor failure analysis, but interpreting its data remains challenging. In practice, measurement noise, caused by complex packaging structures and material variations, can make very similar signals appear different, highlighting the instability of the interpretation process. This talk uses noise in SAM data as an example to illustrate how an AI-driven workflow can improve analysis. It demonstrates how structured data, automated evaluation, and a cloud-based platform can streamline handling, processing, and comparing datasets, enabling faster, more consistent, and reproducible failure analysis in practical workflows.

Failure analysis increasingly depends on high‑resolution imaging, but extracting quantitative information from large datasets is still manual and slow. This talk explores how instance segmentation and other AI methods can add concrete value to failure analysis workflows. We compare classical & AI-based computer vision approaches and discuss their advantages & disadvantages. In a short live demo we will show a few examples from the EU project FA2IR and demonstrate gains in throughput, repeatability and traceability.

Failure analysis in semiconductor manufacturing requires fast and reliable access to many different data sources. As IT environments continue shifting toward cloud‑based solutions, traditional, separate workflows make it difficult to keep analysis efficient and consistent.
In this talk, I will show how combining bitmap data, inline‑defect inspection results, scan‑diagnosis output, FA results , and electrical sort information into one integrated digital workflow, which improves the turnaround time and quality of failure analysis. Automated data alignment and correlation help engineers identify patterns and potential root causes much earlier in the process.
The unified workflow has been demonstrated to reduce manual effort, enhance transparency, and ensure that all relevant information is available when required for failure analysis. This results in faster diagnostics, improved support for engineering teams, and greater customer satisfaction, because decisions can be made based on complete, up‑to‑date data.

Failure analysis (FA) in microelectronics is increasingly challenging due to miniaturization and the need for precise defect localization. Traditional methods rely on manual, time-intensive inspection. We propose a digital workflow using a domain-specific multi-task model for joint detection and segmentation of defect such as voids and cracks. This enables multi-scale learning across devices and resolutions, improving generalization while reducing annotation effort and speeding transfer learning. The developed workflows when validated against expert-annotated data using metrics such as intersection over union (IoU) and F1-score shows detection accuracies of 82–93% across two use cases with varying defect types and imaging conditions. Processing speed improved by over 30x compared to conventional pipelines due to automated feature extraction and reduced model tuning. Results indicate a reduction of over 70% in total effort, primarily due to minimizing the need for extensive pixel-level labeling and eliminating the requirement for separate models for each defect type (e.g. voids). Overall, the approach streamlines FA and enables scalable, high-throughput, data-driven defect analysis.

Semiconductor failure analysis increasingly benefits from machine learning, but individual organizations often lack enough data to build robust and accurate models. At the same time, building databases across companies is typically restricted due to intellectual property and confidentiality concerns. Federated Learning provides a collaborative approach where multiple partners can jointly train a machine learning model without sharing their underlying data. This talk introduces the fundamentals of Federated Learning and explains how it enables failure analysis partners to combine knowledge from distributed datasets while keeping proprietary data local..