Jiaqi Tang

Advanced packages, such as 2.5D and 3D architectures, enable significant improvements in performance and bandwidth, while reducing overall footprint. However, as package complexity increases with multiple dies and components integrated into one package, failure analysis methodologies must evolve to accommodate these changing architectures.
One of the challenges in failure analysis on 2.5D/3D packages is sample preparation; ensuring the region of interest is exposed while minimizing impact on the failure site. This presentation will discuss the application of Microwave Induced Plasma (MIP) in sample preparation workflows, where localized MIP etching is applied from top-down, bottom-up, and cross-sectional approaches. Package-level case studies will cover underfill removal to expose μbump and dies in CoWoS packages, and polyimide removal to expose copper RDL in InFO packages. Latest developments on MIP+ etching for die-level and board-level sample preparation will cover selective Si removal for backside access to Si die, GaN-on-Si die, and bridge die for fault isolation, as well as silicone sealant removal to access components on PCB board and flex cable.

Jiaqi Tang is the CTO of JIACO Instruments, a company he co-founded in 2014 to develop and commercialize Microwave Induced Plasma (MIP) technology for advanced sample preparation in failure analysis of packaged IC devices. With over 17 years of experience, he leads a multidisciplinary team focused on fundamental MIP research and application development, working in close collaboration with industrial users of the MIP systems.
Jiaqi received his Ph.D. in microelectronics from Delft University of Technology, M.Sc. from University of Pennsylvania, and B.Sc. from Fudan University. He has published more than 30 papers and serves on the Technical Program Committee for IPFA and ESREF conferences.