Abstracts by Session

Session A: Introduction and Keynotes
Tues  9:20 – 10:00 Frank Fournel Keynote: Characterisation needs in wafer-to-wafer and die-to-wafer direct bonding

Direct bonding is now a well-established technique that enables various 3D applications. Mass production of silicon dioxide to silicon dioxide bonding, as well as hybrid surfaces with copper pads, is in mass production within microelectronic foundries. However, hydrophilic direct bonding remains a challenging technology due to its very low adhesion energy, necessitating stringent control over surface properties such as flatness, roughness, and particle contamination. Before bonding, precise control of these surface parameters is mandatory.

Furthermore, post-bonding, it is imperative to monitor defectivity with a buried interface between 775µm of silicon. Bonding energy is also a crucial consideration, for which only destructive technology is currently available. Additionally, for in-depth analysis of the bonding interface, techniques such as X-ray, FTIR, or even neutron reflectivity are required.

While there are numerous failure analysis and surface material diagnostic methods at the wafer scale, the complexity significantly increases at the die scale, revealing vast challenges. As die-to-wafer bonding is on the verge of entering mass production, it is high time to extend the same characterization capabilities to this scale.

Tues  10:00 – 10:40 Anton Chichkov Keynote: EU Chips Act – An Introduction

The EU Chips Act represents a critical strategy for enhancing the European Union’s semiconductor capabilities, ensuring technological sovereignty, and fostering innovation. This talk will provide a comprehensive overview of the Chips Joint Undertaking (Chips JU), elucidating its structure, budget, and governance framework. Attendees will gain insights into the specific calls launched under the Chips initiative as well as traditional, non-initiative calls, highlighting their distinct objectives and opportunities. Finally, the session will outline the call schedule and key topics for 2024, preparing stakeholders to effectively engage with forthcoming opportunities.

Session B: Heterogeneous Integration
Tues  11:20 – 11:40 Serena Iacovo A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage

Wafer to wafer bonding studies were carried out on blanket and patterned highly warped wafers using SiCN as bonding dielectric material to gain a deeper understanding of SiCN-to-SiCN direct bonding and to assess the impact of wafer shape on bonding overlay results. Regarding the fundamental understanding of SiCN bonding, characterization data show that the SiCN-to-SiCN interface is oxidized, suggesting strongly bonded due to the presence of covalent bonds, already at room temperature, in contrast to what has been hypothesized for SiO2 for which this reaction would start only by subjecting the bonded pair to an anneal of 150 °C. As concerns the impact of shapes on final bonding results, bonding experiments are carried out by combining different wafer shapes. Tools such as patterned wafer geometry (PWG) and a lithography scanner were used to measure the distortion signature of the wafers before and after bonding. Bonding recipe parameters were optimized to minimize overlay errors, on two different bonding tool configurations, for nominally flat wafers. The same parameters were used to bond the warped wafers to investigate the impact of wafer warpage.

Tues  11:40 – 12:00 Sebastian Quednau Assembly and Interconnection Technology with Nanowires

NanoWired, founded in 2017 as a spin-off from TU Darmstadt, has developed and patented an interconnection technology known as the NanoWiring process. This process allows for the coating of various substrates with copper nanowires. From this foundation, several assembly processes have been derived: KlettWelding, KlettSintering, and KlettGlueing. The versatility of NanoWired’s technologies enables the connection of electronics across a wide range of contact sizes – from several square centimeters for power electronic parts down to microelectronic parts with contact diameters as small as a few micrometers. Remarkably, even highly sensitive components can be connected due to the ability to work at very low temperatures, including room temperature.

In this presentation, NanoWired will present the technology process flows and highlight its applications. Notably, the talk will delve into the use of NanoWired technology in GaN power electronics, exploring how flip chip technologies can enhance high-frequency behavior and reduce Rdson.

Tues  12:00 – 12:20 Torsten Grawunder Open Advanced Packaging / Micro Integration Foundry as a model for one manufacturing platform with integrated LAB-in-the-FAB concept

The chip design process with Chiplets fundamentally changes the meaning and requirements of advanced packaging. Against the background that Swissbit Germany AG acts as a semiconductor backend manufacturer, the technological transformation process (SoC, SiP towards SoP) for advanced manufacturing is described, including the new meaning of Open Advanced Packaging / Micro Integration Foundry as a model for a manufacturing platform with integrated LAB-in-the-FAB concept. The diverse challenges that arise with the central idea of chiplets in relation to D2D bus systems, chiplet frameworks and its underlying design kits (CDK+ADK+WDK+SPDK) and the architectural designs in the chip packaging design process are described. The outstanding importance of integrating a LAB-in-the-FAB concept for a manufacturing platform for chiplets (SiP, SoP) will be presented.

Tues  12:20 – 12:40 Sebastian Brand Approaches in high resolution non-destructive defect localization to meet current and future integration challenges

Increasing miniaturization combined with steadily increasing complexity in interconnect technology and integration of new package and semiconductor materials highly challenge non-destructive inspection and quality assessment methods, necessary for defect reduction and reliability. General applicability of machine learning based data processing has been demonstrated and proven effective in various tasks related to the microelectronic failure analysis. However, to reach the next level of implementation into the everyday workflows and to obtain a broad acceptance further development beyond the state of the art will be necessary. The present paper will describe the gap between existing solutions and the necessary requirements to decrease the operator’s subjectivity and to increase the level of autonomy and automation for the application in high-resolution non-destructive defect detection and localization. Equipment related transfer characteristics in the acquired measurement data need to be removed for a generalized application and compatibility between different tools and to increase to degree of work-flow automation. On the other side specific sample related features in the data will require specifically trained models and thus reduce the possible level of generalization. The paper will introduce novel concepts for removing specificities of the equipment and samples, concepts for deviation-based defect tracing as well as feast and efficient computing to allow for further automation of data and signal analysis in microelectronics failure identification and characterization.

Tues  12:40 – 13:00 Jan Proschwitz Robustness and reliability testing for heterointegration

Heterogeneous integration of chiplets enables complex and compact electronic systems by breaking the limits of reticle size. This is achieved by combining function-optimized wafer technologies with manufacturing yield improvements. Over the past few years, different 2.XD and 3D packaging architectures have been developed and introduced for high performance compute applications as well as commercial products. However, the complexity of such advanced package constructions leads to new challenges for managing the intrinsic mechanical stress as well as for adapted electrical test strategies. The presentation will give an overview of these challenges and how robustness can be improved and how product validation can be implemented.

Tues  13:00 – 13:20 Dirk Schade Revolutionizing semiconductor testing: The power of automation in testing chiplets

The rapid evolution of semiconductor technology has given rise to novel paradigms in chip design and manufacturing. Such innovation is the concept of chiplets, which involves breaking down a complex integrated circuit into smaller, interconnected components, each designed to perform specific functions. This article delves into the world of chiplets and their intrinsic connection to material testing. Chiplets offer numerous advantages, including enhanced flexibility, scalability, and cost-effectiveness in semiconductor design. However, the successful implementation of chiplets hinges on rigorous material testing and characterization to ensure reliability and performance. In conclusion, chiplets represent a transformative approach to semiconductor design, offering unparalleled opportunities for innovation and customization. However, the realization of their full potential relies heavily on robust material testing and characterization processes. This abstract underscores the critical relationship between chiplets and material testing, highlighting the challenges and advancements in this dynamic field that pave the way for the next generation of electronic devices.

Session C: Novel Failure Analysis Techniques
Tues  14:40 – 15:00 Sven Kayser Hybrid SIMS: New possibilities for advanced semiconductor structure analysis with Self-Focusing SIMS

To boost the performances of the next generation transistors, new materials and device architectures have been investigated in the semiconductor industries. In this context, strained-Ge and SiGe channel FET’s have received high interest.

As a consequence, characterization techniques have to provide chemical information and high sensitivity with a spatial resolution compatible with the device structure of down to 10 nm. Secondary Ion Mass Spectrometry (SIMS) provides excellent chemical information and low detection limits, but lacks the spatial resolution to directly probe devices from sub-10 nm technologies. Nevertheless, its applicability to analyze the composition of narrow trenches (< 20nm) has been enabled through the concept of Self-Focusing SIMS (SF-SIMS).

In this contribution, we will show that the improved mass resolution of the recently developed Hybrid SIMS instrument, using the Orbitrap™ mass analyzer in a SIMS instrument, is extremely beneficial for advanced semiconductor structure analysis.

Tues  15:00 – 15:20 Wenbing Yun X-ray Assisted Device Alteration (XADA) for Future Generations of ICs with Backside Power Distribution Network

Backside power delivery (BPD) is widely anticipated by the semiconductor industry, enabling more efficient power delivery and significant improvements to transistor density. The challenge with BPD is that existing circuit debugging / fault isolation techniques such as LADA (laser assisted device alteration) will become obsolete. Because LADA requires backside silicon thinning, the shift to BPD in which power rails are placed on the backside means this approach will no longer work. One of the most promising approaches to address emerging BPD schemes. is using focused X-rays instead of NIR in a newly developed approach called X-ray Assisted Device Alteration (XADA). Because X-rays are sufficiently transmissive to Cu and Si, little to no sample preparation including backside thinning is required and the intact device can be probed. Recent work has demonstrated the effectiveness of using focused x-rays from a laboratory source for altering transistor threshold voltages (VT), changing ring oscillator (RO) frequencies and inducing timing shifts, including the localization of a physical defect using a real-world chip. Roadmap for smaller X-ray probe size to < 1 um will be discussed.

Tues  15:20 – 15:40 Rene Hammer Advances in EFA with color coded multi-channel nanoprobing

Key improvements to data acquisition, visualization and analysis are presented for Electrical Failure Analysis (EFA). Multi-channel image acquisition is introduced, where every nanoprobe is used for simultaneous imaging, in combination with color coding either by probe or by current. This new approach improves visualization of new device technologies with increasing three-dimensional complexity, in particular for overlapping structures and fields. Further, this new multichannel method opens opportunities for image mixing to improve data quality and signal interpretation.

Tues  15:40 – 16:00 Thomas Adlmaier Advancing the Quantification Workflow for 2D Charge Carrier Profiling by Scanning Spreading Resistance Microscopy

SSRM (Scanning Spreading Resistance Microscopy) is an established technique for 2D dopant visualization with high lateral resolution (~1-10nm) and sensitivity (~1E14-1E20 1/cm³). While normal SSRM produces qualitative information about doping shapes and sizes, quantitative SSRM adds a calibration measurement on a known dopant reference to extract absolute values on top. While this approach seems easy in theory, in actual practice one is met with numerous complications, often leading to a long and costly analysis. To alleviate such complications, we introduce two innovations: Firstly, we propose a novel Partial-Staircase (PSC) dopant reference profile which combines the advantages of the conventional staircase profiles and sole reference implants into one. Secondly an extended sample preparation workflow is presented, which brings area of interest and dopant reference into high proximity and enforces the exact same measurement conditions on both by design. Put together, both innovations reduce analysis complexity while increasing quantification accuracy.

Tues  16:00 – 16:20 Anjanashree MR Sharma FA methodologies for silicon photonics devices

Photonic integrated circuits (PICs) developed on silicon photonics (SiPh) platforms are a significant breakthrough in the field of data communication as they increase the speed and capacity of data transmission with lesser power consumption. It integrates devices such as lasers, photodetectors, optical waveguides, and modulators on the silicon substrate and can be fabricated using an industry-standard CMOS process. This has pushed SiPh devices into the commercial manufacturing phase. Hence, it is very relevant to perform the failure analysis (FA) to ensure the reliability of these devices. In my presentation, I will discuss the FA methodologies used for defect localization in emerging devices used in PICs such as photodetectors and laser diodes, fabricated at imec. In particular, germanium photodetectors and InGaAs/GaAs nano-ridge p-i-n diodes which are extensively researched and have the potential to be adapted in the industry, are used as test devices for this study. The application of conventional and advanced FA techniques such as lock-in thermography (LIT), thermoreflectance, and electron beam-based nanoprobing based on their spatial resolution will be discussed.

Session D: Panel Discussion
Tues  17:00 – 18:00 Keith Serrels I Libor Strakoš I Chris Richardson I Martin Igarashi I Lukáš Hladík I Wenbing Yun I Thomas Rodgers I Peter Hoffrogge Failure Analysis roadmap status & vendor feedback

The FA Technology Roadmap initiative, which is driven by ASM’s Electronic Device Failure Analysis Society (EDFAS) Society, is actively involved to identify the longer term needs and gaps of failure analysis methods and equipment related to new trends in semiconductor device manufacturing. The purpose of the FA Technology Roadmap is to leverage the technical expertise captured throughout the industry to identify both current and future FA challenges and to serve as an international technical platform for failure analysis. The goal is to bridge existing and upcoming gaps by leveraging both the expertise of equipment providers and the research conducted in academic labs.

Last year, during the panel discussion, the invited panelists provided a summary of the progress made in the FA Technology Roadmap activities. They highlighted the ongoing efforts to identify and analyze the current and future FA challenges. This involved conducting an industry-wide gap analysis, which helped in mapping out the areas that require further attention and improvement.

This year, the focus is on the vendor’s responses to the industry-wide gap analysis survey. The committee is actively seeking input and feedback from equipment providers to gain insights into their perspectives on the identified gaps. This will enable the committee to gather valuable information on potential solutions and innovations that can address the challenges faced by the industry.

The FA Technology Roadmap Committee recognizes the importance of collaboration and knowledge-sharing between equipment providers, academic labs, and other stakeholders in the FA industry. By working together, they aim to drive advancements and improvements in FA techniques, tools and workflows.

Session E: Tutorial
Wed  08:00 – 09:00 Michael Kögel Tutorial: Machine Learning Based Data and Signal Analysis Methods for the Application in Failure Analysis

Since its release, ChatGPT has sparked ongoing fascination for its human-like responses, reflecting the growing interest in AI’s potential applications across various fields. In microelectronics failure analysis, a discipline aiming for reliability and performance improvement, machine learning holds promise by aiding defect localization and subsequent analysis through destructive inspection tools. The ability to process large datasets and extract correlated information benefits defect analysis, assisting in identifying root causes.

This tutorial introduces machine learning and deep learning to failure analysts covering historical context, data handling, feature extraction, learning algorithms, model evaluation, and optimization. It explores convolutional neural networks for image processing and advanced neural network applications like auto-encoders and natural language processing. Case studies demonstrate ML’s potential in failure analysis, such as bill of material generation from optical images, automatic defect detection on PCBs, void segmentation in x-ray images, and SEM image denoising.


Session F: SiC & GaN Power Electronics
Wed  9:40 – 10:20 Peter Friedrichs Keynote: SiC power devices and related robustness and reliability aspects

The implementation of wide band gap based power semiconductor solutions, was growing substantially during the last years, Driving forces behind this market development are global megatrends like energy saving, de-carbonization and effective use of scarce resources. One of the success factors of implementing SiC as a power device material is the chance to adopt many of the well-known device concepts and processing technologies from silicon.

Thus, many of the procedures used to verify the long-term stability of silicon devices could be transferred to SiC. Nevertheless, a deeper analysis has shown that SiC based devices require some additional and different reliability tests compared to Si based devices. Aspects like anisotropic material properties, higher electric fields or faster transients may have an influence on nearly all established qualification tests.

Furthermore, for many existing qualification standards that specify accelerated tests, models are used to extrapolate the test data and correlate it to real world application conditions. These model parameters need to be verified for their application and accuracy with respect to SiC. The keynote presentation will give a more detailed inside into the current status of SiC related reliability assurance
procedures, also addressing ruggedness aspects.

Wed  10:20 – 10:40 Thorsten Vehoff Robustness for power electronic packaging

In recent years, high power electronics has become one of the fastest growing market segments of the semiconductor industry. The adoption of SiC device technology has enabled a substantial increase in power density of power module performance. However, the traditional power module assembly materials have been recognized as a technical barrier in moving to a higher performance system due to inherent limitations. To achieve this, packaging design is key, to get high efficiency modules taking advantage of wide band gap materials such as silicon carbide (SiC) and gallium nitride (GaN) devices. The features of these devices pose substantial challenges including fast switching speed and heat dissipation. The development of novel packaging techniques is needed to overcome new challenges such as material selection and packaging processes to improve performance, efficiency, and reliability of the power module assembly.

New innovative packaging material solutions such as Ag and Cu sintering, die top system, Power soft Cu wires/ ribbons, and Ag free AMB Silicon nitride substrate will be discussed in this presentation. These materials significantly improve efficiency and reliability of power module performance. Furthermore, some of the reliability test data will be highlighted.

Wed  10:40 – 11:00 Dick Scholten Gate-switching instability in silicon carbide power MOSFET’s

Threshold voltage drift in MOSFET’s due to prolonged application of a high constant gate voltage at high temperature is a well-known degradation mechanism and has been observed in MOSFET-technologies based on silicon, gallium nitride, or silicon carbide.  A peculiarity of silicon carbide MOSFET’s is that high numbers of bipolar gate switching events result in a threshold voltage drift that exceeds the drift expected from constant voltage stress alone. The presentation will detail the properties of this degradation mechanism and will give an overview of possible root causes currently under discussion. Arguments to test worst case scenarios on chip level rather than on module level will be discussed.

Wed  11:00 – 11:20 Andreas Graff Integration of free-standing single crystal diamond (SCD) nanomembranes in ultra-wide bandgap electronics

Single crystal diamond (SCD) has great potential for next-generation RF and power electronics, because of the excellent thermal conductivity and high carrier mobility. Toward the realization of high-performance ultra-wide bandgap (UWBG) electronics, it is crucial to create p-n junctions by complementing p-type property of SCD with n-type property of other UWBG. Free-standing SCD nanomembranes (NMs), enables us to heterogeneously integrate SCD with other UWBG semiconductors via a semiconductor bonding technology. SCD NMs technology and hetero-integration technology will be discussed covering the fabrication process and material properties of SCD NMs, as well as the device manufacturing process and electrical property of SCD NM / Ga2O3 heterojunction p-n diodes.

Doped and undoped SCD epitaxy layers were deposited on (001) SCD wafers. Hydrogen implantation was performed to separate the structured top portion of the SCD which then becomes NMs after a post annealing process. The released SCD NMs were transferred to n-/n+ Ga2O3 epitaxy wafer via a micro-transfer printing process to create SCD NM/ Ga2O3 heterojunction p-n diodes. The device exhibited excellent electrical properties. The breakdown electrical field was measured to exceed 2MV/cm at room temperature, demonstrating the superior performance of the UWBG p-n heterojunction diode based on SCD NM technology.

Wed  11:20 – 11:40 Antoine Reverdy Power devices Failure Analysis Use Cases Using High voltage OBIRCh workflows

Nowadays, electrification trends, especially in the automotive market, are driving the need for high power electronics. In the past years, Silicon Carbide (SiC) and Gallium Nitride (GaN) microelectronics solutions have been introduced on the market as they have clear benefits for such application (its key benefits include delivering higher voltage operation, wider temperature ranges and increased switching frequencies). These Wide Band Gap (WBG) technologies are relatively new, thus, quality control and reliability understanding are critical topics to make sure they will remain sustainable.

We will present 3 Failure Analysis use cases and workflows related to power device technologies. In collaboration with our Fault Isolation tool equipment supplier (ThermoFisher Scientific), we have developed a High Voltage solution to address HV-O.B.I.R.Ch. and HV-Photoemission analysis on our Meridian S Platform. This solution allows addressing our current High Power devices roadmap up to 3kV.

Session G: Failure Analysis Workflows and Digitalization
Wed 13:00 – 13:40 Prof. Dr. Zhiheng Huang Keynote:  Applied Microstructure for AI: From Electrons to Devices & From Diagnostics to Informatics

Although not even mentioned in the original launch of the US materials genome initiative (MGI) in 2011, AI has now been identified the true enabler and driving force of MGI.Latest progress reports Google DeepMind and robots joined forces to discover and synthesis new materials. Microstructure of materials should be treated as a system as perceived by the pioneering work of C.S. Smith. Highlighting the achievements of MGI in the past decade, it is the atomic scale details represented by DFT-based calculations and graph neural network that have attracted most of the interests. Phase spaces that reflect elemental combinations to yield desirable chemistry or physics have been explored, but the results that AI recommends still deserve better interpretations. Based on a convergence amongst deep neural networks, wavelets, and physiology of human brain, and the theory of Mallat Scattering Transform, this talk introduces the principles behind the recent proposed Microstructure Hierarchy Descriptor (μSHD). The μSHDs are designable and reduced order indices that can be used to establish quantitative linkages between structures, properties, and failure analyses. Applied microstructure diagnostics spanning structures from electron to device levels, and failure analyses on 3D and power electronics will be discussed with a vision from μSHD data to microstructure informatics and AI.

Wed  13:40 – 14:00 Allen Gu An Artificial Intelligence Powered Reconstruction and Metrology Workflow for Semiconductor Packaging Development using High-Resolution 3D X-ray Microscopy

Over the past decade, the innovations in semiconductor packaging have been the catalyst to improve electronics device performance. Among many rapidly emerged package architectures, 3D multi-chip stacking and heterogenous integration become particularly attractive for the capabilities to increase I/O density, save power consumption and shorten the time to market. However, the IC packaging industry faces the challenge to find an effective inspection and metrology solution for these innovative packages. 3D X-ray microscopy (XRM) technique has been rapidly and widely adopted to failure analysis labs in semiconductor community [1-2]. With its non-destructive and high resolution imaging capabilities, deeply buried defects can be visualized and analyzed prior to physical cross-section. In this paper, we propose a novel imaging and quantification workflow to enable 3D structural measurements using the 3D XRM imaging technique. The test vehicle was a multi-die coupon with 15-layer stacks for each die. The fabrication process started with the IMEC’s flip chip fan-out wafer level packaging (FO-WLP) process flow to connect a thin Si bridge to the logic die substrate. A standard thermal compression bonding (TCB) process was followed to complete the delicate die attachment. To validate the die placement accuracy and bond line thickness uniformity, a measurement workflow is required to evaluate and optimize bonding quality and process flow.

Wed  14:00 – 14:20 Amit Kumar Choudhary ML assisted defect detection for reliable failure analysis in microelectronic components

Microelectronic products from the semiconductor industry are crucial for many recent technological advances in automotive industries and intelligent production systems but have reliability issues that require failure analysis to investigate the failures’ root cause. Using visual inspection systems such as cameras or microscopes, images of microelectronic products or components are acquired to be evaluated for potential defects and anomalies arising from the manufacturing process. Manual evaluation of such a large amount of data carries the risk of subjective errors, consumes lot of time and efforts, leading to backlogs that can drive costs.

In this work, we developed defect detection models using advanced machine learning and computer vision approaches that are more reliable, with detection accuracy close to or sometimes better than manual or existing approaches. The developed models for different use-cases (voids, phases, anomalies), have an accuracy ranging from 86 % to 94 % and has advantage of being time-efficient by a factor of 20x to 30x for different tasks. Each use-case involves image data from various microscopy techniques such as OM, SEM, X-ray and SAM.

Wed  14:20 – 14:40 Fabian Rudau In Depth Logic Analysis on Digital Designs

Physical failure analysis (physical FA) for automotive devices requires an efficient FA workflow to satisfy the customer’s expectations of on-time-delivery and success rate. Field return complaints typically contain only one single failing device. Hence, every step in fault isolation and physical preparation requires a high confidence level in order to avoid the risk of losing the failure in subsequent destructive steps.
We will present a software to support the FA engineer to quickly identify correct and incorrect logic signals in digital circuits enabling fast and successful FA.

Wed  14:40 – 15:00 Christian Hollerith Integrated Workflows for Failure Analysis

In EU-funding project FA4.0, the idea of Integrated Workflows within FA has been defined and is being developed. Integrated Workflows in FA means that sample remains on the same sample holder in a whole workflow and data, especially position data of regions of interest, es being transported from tool to tool to simplify the workflows for the user as well as increase efficiency. To enable these workflows on tools of different vendors, exchange formats for data as well as a common universal sample holder has to be defined which is established also as industrial standard. This presentation will show an example how this principle can work including a TePLA-SAM and a Tescan-PFIB and also of the necessary standardization process in cooperation with SEMI.

Wed  15:00 – 15:20 Libor Strakoš In-situ AFM-in-(FIB)SEM workflow for site-specific & correlative failure analysis of semiconductors

The AFM-in-SEM approach combines Atomic Force Microscopy (AFM)-based techniques with Scanning Electron Microscopy (SEM)-based or Focused Ion Beam FIB-SEM based techniques. It provides a means to integrated correlative approach for studying semiconductor materials and devices. This solution allows for the non-destructive mapping of diverse electrical properties of trenches, measuring gate dimensions or localizing defects, which could help to understand the device processes. This approach provides the advantages of combining the benefits of capabilities of site-specific sample preparation by FIB, ultra high-resolution imaging by SEM and AFM techniques. The integration offers additional benefits, including measuring properties at the exact location under in-situ conditions and avoiding sample or environmental changes such as differential pressure or sample contamination. Typical example of such site specific analysis is dopant concentration profiling on the level of individual device.

Wed  15:20 – 15:40 Oscar Recalde Automated SEM/EBIC workflows for wafer level failure analysis

In semiconductor electronics, efficient failure analysis is crucial for reliability. Here, we present an automated workflow for precise and rapid failure analysis. Optimizing probe placement significantly cuts analysis time while improving result reliability, which is particularly beneficial for beginner nanoprobing users.
In a proof-of-concept experiment, the probe alignment and landing process was successfully achieved through a few clicks. Our study demonstrates that this process can be successfully executed not only at high electron beam energy voltages but also at low electron beam voltages, ensuring versatility and robustness in failure analysis workflows.
Furthermore, our study introduces a semi-automated failure analysis workflow incorporating encoded micromanipulators for examining devices down to 3 nm. All this, coupled with advanced data processing integrated into the Kleindiek Advanced Probing Tool software and Electron Beam Induced Current (EBIC) analysis, enables comprehensive characterization of device failures. An automated workflow signifies a significant advancement in semiconductor failure analysis for improved reliability and innovation.