Tavousi

19. May 2026 14:20 – 14:40 3D Heterogeneous Integration Tescan FemtoChisel: High-Throughput Decapsulation, Delayering, and Large-Area Cross-Sectioning for Advanced Microelectronics Pouya Tavousi Tescan I US Abstract Advanced microelectronics failure analysis and metrology require rapid access through heterogeneous stacks (mold compound, underfill, metals, dielectrics, silicon). Tescan FemtoChisel is an ultrashort-pulsed laser platform for high-throughput sample preparation,…

Holten

20. May 2026 10:20 – 10:40 Advanced Failure Analyse Techniques Quantum Magnetic Microscopy for Semiconductor Failure Analysis Marvin Holten DiaSense ApS I Denmark Abstract The transition to advanced 3D integrated circuits and system-in-package designs is creating major challenges for fault detection, yield optimisation, and process understanding. Existing inspection and failure-analysis methods often cannot provide the…

Svenningsson

20. May 2026 15:20 – 15:40 Artificial Intelligence and Digitalization Federated Learning for Semiconductor Failure Analysis Leo Svenningsson RISE I Sweden Abstract Semiconductor failure analysis increasingly benefits from machine learning, but individual organizations often lack enough data to build robust and accurate models. At the same time, building databases across companies is typically restricted due…

Tang

19. May 2026 14:00 – 14:20 3D Heterogeneous Integration Microwave Induced Plasma Etching for 2.5D/3D Advanced Package Sample Preparation Jiaqi Tang JIACO Instruments I The Netherlands Abstract Advanced packages, such as 2.5D and 3D architectures, enable significant improvements in performance and bandwidth, while reducing overall footprint. However, as package complexity increases with multiple dies and…

Choudhary

20. May 2026 15:00 – 15:20 Artificial Intelligence and Digitalization Accelerating and standardization of failure analysis through digital workflows and machine learning Amit Choudhary Matworks GmbH I Germany Abstract Failure analysis (FA) in microelectronics is increasingly challenging due to miniaturization and the need for precise defect localization. Traditional methods rely on manual, time-intensive inspection. We…

Sweeney

19. May 2026 11:40 – 12:00 3D Heterogeneous Integration Failure Analysis Techniques and Lab Requirements for Silicon Photonics Fault Isolation Ryan Sweeney Globalfoundries I US Abstract As industries expand their use of silicon photonic integrated circuits (PICs), it is imperative that manufacturers be able to continuously improve the quality of their manufactured PICs. To do…

Fichtl

20. May 2026 14:20 – 14:40 Artificial Intelligence and Digitalization Exploring the value of instance segmentation & other AI methods for Failure Analysis Bernhard Fichtl Carl Zeiss Microscopy GmbH I Germany Abstract Failure analysis increasingly depends on high‑resolution imaging, but extracting quantitative information from large datasets is still manual and slow. This talk explores how…

Muehle

19. May 2026 16:20 – 16:40 Wide Bandgap Technolgies Diamond-based technologies for active device and thermal cooling integration Matthias Muehle Fraunhofer CMW I US Abstract Diamond is an ultra-wide bandgap semiconductor material, whose electric properties make it a great choice as p-type material for device integration. Further, diamond possesses the highest thermal conductivity, which also…

Li

20. May 2026 11:40 – 12:00 Advanced Failure Analyse Techniques Ultra-Thin Ga-Free Lamella Preparation Enabling Pristine Structural-Chemical Analysis of Advanced Technology Nodes Letian Li ThermoFisher Scientific I The Netherlands Abstract Ultra-thin, precisely targeted lamella preparation on advanced IC devices has traditionally been considered a Ga-FIB application. However, recent advances in semiconductor processing now require gallium-free…

Bisgin

19. May 2026 13:40 – 14:00 3D Heterogeneous Integration Quantum Diamond Microscopy for Non-Destructive Failure Analysis of an Integrated Fan-Out Package-on-Package iPhone Chip Bartu Bisgin QuantumDiamonds GmbH I Germany Abstract The increasing complexity of advanced semiconductor packages, driven by chiplet architectures and 2.5D/3D integration, challenges conventional failure localization methods such as lock-in thermography (LIT) and…